The GPIO_SET_PLS_CNT_CFG command allows to configure pulse counter module, to start, stop and suspend pulse counting and to set the conditions of the event generation.
| Byte 0 | GPIO_SET_PLS_CNT_CFG | Command ID (must be 0x1D). | |
| Byte 1 | ECHO | Echo to associate the command with the response. | |
| Byte 2 | Bits 7..3 | Reserved | Reserved (must be 0). |
| Bit 2 | SUSPENDED | Pulse counter state (suspended or not). | |
| Bit 1 | ON | Pulse counter switcher (used to start/stop pulse counting). | |
| Bit 0 | PLS_CNT_NUMBER | ID number of the counter to count pulses. | |
| Byte 3 | Bits 7..4 | PLS_CNT_MODE | Pulse counter mode. |
| Bit 3 | Reserved | Reserved (must be 0). | |
| Bit 2 | EV_MATCH | Matcher (an event will be sent when counter limits are exceeded). | |
| Bit 1 | Reserved | Reserved (must be 0). | |
| Bit 0 | EV_OVERFLOW | Matcher (an event will be sent when maximum number of pulses is detected). | |
| Byte 4 | REPEAT | Repeat interval value in units of 10 ms. | |
| Byte 5 | LIMIT[2] | Counter limit (time period or threshold number of pulses). | |
| Byte 6 | LIMIT[1] | ||
| Byte 7 | LIMIT[0] | ||
Command is an 8-byte array of the following format:
This byte contains command ID (command type). It must be set to 0x1D.
This byte is used to associate a response received from GPIO-24 adapter with a specific command. Response will contain exactly the same value in its echo byte.
| Bits 7..3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|
| Reserved | SUSPENDED | ON | PLS_CNT_NUMBER |
These bits are reserved for future usage. They must be set to 0.
Pulse counter state:
0 – pulse counter runs immediately after configuration.
1 – pulse counter will be in suspended state. It will not run until you send the GPIO_RESUME_PLS_CNT command.
The pulse counter state (on/off):
1 – the pin is switched to the pulse counter mode. GPIO_GET_CFG and GPIO_GET_PIN_CFG commands will return GPIO_CFG_PLS_CNT (0x7) value for the pin. The pin can be used only by the pulse counter module;
0 – the pulse counter mode is switched off on the pin. GPIO_GET_CFG and GPIO_GET_PIN_CFG commands will return GPIO_CFG_NOT_CONFIGURED (0xf) value for the pin. The pin can be used by any module.
The ID number of the pulse counter:
0 – pulse counter on A.3 pin;
1 – pulse counter on A.4 pin.
| Bits 7..4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|
| PLS_CNT_MODE | Reserved | EV_MATCH | Reserved | EV_OVERFLOW |
The pulse counter can be configured into one of three possible modes:
GPIO_PLS_CNT_MODE_FREE_RUN(0) – pulses are counted until maximum number of pulses (16,777,215) is reached. For more detailed information see Section 11.1.1, “Free Run Mode”.
GPIO_PLS_CNT_MODE_TIME_BASED(1) – pulses are counted only during user-defined time period. For more detailed information see Section 11.1.2, “Time Based Mode”.
GPIO_PLS_CNT_MODE_PULSE_BASED(2) – pulses are counted until user-defined number of pulses is detected. For more detailed information see Section 11.1.3, “Pulse Based Mode”.
This bit is reserved for future usage. It must be set to 0.
1 – USB-I/O adapter will send
the GPIO_EV_PLS_CNT event either when the time
period is exceeded (Time Based
Mode) or when the threshold number of
pulses is detected (Pulse Based
Mode). For more detailed information see
Section 11.2, “Pulse Counter Event”;
0 – the event is not generated when pulse counter limits are reached.
This bit is not used in Free Run Mode and must be set to 0.
This bit is reserved for future usage and must be set to 0.
1 – USB-I/O adapter will send
the GPIO_EV_PLS_CNT event when maximum number
of pulses is reached. For more detailed information
see Section 11.2, “Pulse Counter Event”;
0 – the event is not generated when maximum number of pulses is reached.
This byte defines the repeat interval for GPIO_EV_PLS_CNT event generation. If this byte is non-zero, GPIO-24 adapter sends events each REPEAT*10 ms. For more detailed information see Section 11.2, “Pulse Counter Event”.
These bytes define pulse counter limits.
For the pulse counter in Time Based Mode these bytes define the time period in units of 10 ms up to 16,777,215 (167,772,150 ms or 46.5 h). Pulses will be counted only during this time period.
For the pulse counter in Pulse Based Mode these bytes define the threshold number of pulses up to 16,777,215. Pulses will be counted until this number is detected.
Byte 5: LIMIT[2] – least significant byte (low byte) of a pulse counter limit.
Byte 6: LIMIT[1] – middle byte of threshold a pulse counter limit.
Byte 7: LIMIT[0] – most significant byte (high byte) of a pulse counter limit.
For the pulse counter in Free Run Mode these bytes are not used and must be set to 0.
For convenience GPIO_SET_PLS_CNT_CFG_CMD structure is declared in reports.h file.
GPIO-24 adapter sends GPIO_SET_PLS_CNT_CFG response after command execution.
| Byte 0 | GPIO_SET_PLS_CNT_CFG | Response ID (0x1D). |
| Byte 1 | ECHO | Echo to associate command with the response. |
| Byte 2 | ST | Command execution status. |
| Bytes 3..7 | Reserved | Reserved. |
Response is an 8-byte array of the following format:
Response ID (response type). This byte will contain 0x1D.
Echo byte copied from the corresponding command. It is used to associate the response with the specific command.
Status of the command execution:
GPIO_ST_SUCCESS (0x00) – Pulse counter has succesfully been configured;
GPIO_ST_INVALID_PARAMETER (0x0A) – Unsupported pulse counter mode has been specified.
These bytes are reserved for future usage.
For convenience GPIO_SET_PLS_CNT_CFG_RSP structure is declared in reports.h file.