The GPIO_GET_PIN_CFG command retrieves the configuration
settings for specified I/O pin. I/O pin number
is specified in Byte 2.
| Byte 0 | GPIO_GET_PIN_CFG | Command ID (0x2D). |
| Byte 1 | ECHO | Echo to associate a command with the response. |
| Byte 2 | GPIO | I/O pin number. |
| Bytes 3..7 | Reserved | Reserved (must be 0). |
Command is an 8-byte array of the following format:
This byte contains command ID (command type). It should be set to 0x2D.
This byte is used to associate a response received from GPIO-24 adapter with a specific command. Response will contain exactly the same value in its echo byte.
GPIO pin number:
0..7 corresponds to GPIO PORT A pins 0..7;
8..15 corresponds to GPIO PORT B pins 0..7;
16..23 corresponds to GPIO PORT C pins 0..7.
These bytes are reserved for future usage and must be set to 0.
GPIO-24 adapter sends GPIO_GET_PIN_CFG response after command execution. The configuration settings are specified inside the response.
| Byte 0 | GPIO_GET_PIN_CFG | Response ID (0x2D). |
| Byte 1 | ECHO | Echo to associate a command with the response. |
| Byte 2 | ST | Command execution status. |
| Byte 3 | GPIO | Current GPIO pin number. |
| Byte 4 | CFG | Configuration settings for a specific pin. |
| Byte 5 | EXTENDED_CFG | Extended configuration settings for a specific pin. |
| Byte 6..7 | Reserved | Reserved |
Response is an 8-byte array of the following format:
Response ID (response type). This byte will contain 0x2D.
This byte is used to associate a response received from GPIO-24 adapter with a specific command. Response will contain exactly the same value in its echo byte.
Status of the command execution:
GPIO_ST_SUCCESS (0x0) –
The I/O pin configuration settings were
successfully retrieved;
GPIO_ST_INVALID_GPIO
(0x2) – Invalid I/O pin
number has been specified.
GPIO pin number:
0..7 corresponds to GPIO PORT A pins 0..7;
8..15 corresponds to GPIO PORT B pins 0..7;
16..23 corresponds to GPIO PORT C pins 0..7.
CFG byte contains configuration settings for a specific pin. The following values are supported:
GPIO_CFG_IN (0x0) – I/O pin is configured as a digital input;
GPIO_CFG_OUT (0x1) – I/O pin is configured as a digital output;
GPIO_CFG_PWM (0x2) – I/O pin is configured for PWM (Pulse Width Modulation) output;
GPIO_CFG_PULSE (0x3) – I/O pin is configured to send single pulses. Byte 5:
EXTENDED_CFG contains extended configuration
settings;
GPIO_CFG_ADC (0x4) – I/O pin is used as an analog input by ADC module. Byte 5:
EXTENDED_CFG contains extended configuration
settings;
GPIO_CFG_CMP (0x5) – I/O pin is used by comparator module.
Byte 5:
EXTENDED_CFG contains extended configuration
settings;
GPIO_CFG_FR_CNT (0x6) – I/O pin is used by frequency
counter;
GPIO_CFG_PLS_CNT (0x7) – I/O pin is used by pulse counter;
GPIO_CFG_HPWM (0x8) –
I/O pin is configured for HPWM (High Frequency Pulse Width
Modulation) output;
GPIO_CFG_NOT_CONFIGURED
(0xf) – I/O pin is not
configured.
EXTENDED_CFG byte contains extended configuration settings for a specific pin. The following values are supported:
Extended configuration settings for pins used by the comparator module (these settings are available only when Byte 4: CFG contains GPIO_CFG_CMP (0x5) value):
GPIO_CFG_CMP_IN_MINUS
(0x0) – I/O pin is
configured as VIN- comparator analog
input;
GPIO_CFG_CMP_IN_PLUS (0x1)
– I/O pin is configured as
VIN+ comparator analog
input;
GPIO_CFG_CMP_OUT (0x2)
– I/O pin is configured as comparator
digital output;
GPIO_CFG_CMP_NC (0x3)
– I/O is not connected to a
comparator;
GPIO_CFG_CMP_VREF_HIGH
(0x4) – I/O pin is
configured as High Level Reference Voltage input;
GPIO_CFG_CMP_VREF_LOW
(0x5) – I/O pin is
configured as Low Level Reference Voltage input;
GPIO_CFG_CMP_OUT_VREF
(0x6) – I/O pin is
configured as Comparator Voltage Reference Voltage Module
output.
Extended configuration settings for for pins used by ADC module (these settings are available only when Byte 4: CFG contains GPIO_CFG_ADC (0x4) value):
GPIO_CFG_ADC_IN (0x0) –
I/O pin is configured as ADC analog
input;
GPIO_CFG_ADC_VREF_HIGH
(0x1) – I/O pin is
configured as High Level Reference Voltage input;
GPIO_CFG_ADC_VREF_LOW
(0x2) – I/O pin is
configured as Low Level Reference Voltage input.
Extended configuration settings for pins used to send single pulses (these settings are available only when Byte 4: CFG contains GPIO_CFG_PULSE (0x3) value):
GPIO_CFG_PULSE_ACTIVE
(0x00) – I/O pin is
sending a single pulse at the moment;
GPIO_CFG_PULSE_IDLE
(0x01) – I/O pin is
configured to send single pulses, but it is not sending a
pulse at the moment.
These bytes are reserved for future usage.