SPI Master Interface

All DLN-series adapters are equipped with at least one SPI master module. It performs either full duplex or half duplex synchronous data transfers with configurable frame size. Clock polarity (CPOL) and clock phase (CPHA) can be specified to accommodate all SPI clocking modes. Controlled by PC software, the slave select signal can be configured to control one or more SPI Slave devices.

Asynchronous SPI Master Interface

While DLN series adapters differ in supported SPI master frequencies, all of them benefit from the asynchronous nature of the DLN API. The asynchronous interface introduces significant increase in SPI transfer bandwidth.

SPI master adapters from other vendors suffer from 1 millisecond delay between successive buffers. This delay is caused by the internal limitation of the USB bus. The USB bus divides continuous transfer into 1 millisecond frames. The data to be sent during the frame must be available before the start of sending. When you send data over SPI bus synchronously, you can't send the next buffer until previous buffer is received and acknowledged by the SPI master adapter. This means that you can't send data faster than one buffer in 1 millisecond.

DLN series adapters support both synchronous and asynchronous SPI master interfaces. With asynchronous interface you can send several buffers within one USB frame. All the buffers are delivered to USB host controller driver before the frame starts, so it can transfer all of them within the same USB frame.

  • SPI Master Interface Configuration

    • By using the SPI Interface you can operate with a single master device. The creation of a multi-master SPI system is also possible.

    To start a communication, the master device configures the serial clock (SCK), using a frequency less than or equal to the maximum frequency the slave device supports. SPI Bus Host Adapter supports SPI Interface frequencies as 12 MHz, 3 MHz, 1.5 MHz and less. The SCK logic signal always sent from master device and input to all slave devices. It means that the master device generates the clock signal while sending data. The master device is the active part in the system and always has to provide the clock signal a serial data transmission is based on. You can also configure the clock polarity (CPOL) and the clock phase (CPHA). To configure these parameters you can use DlnSpiMasterSetMode() function. To get SPI Bus Host Adapter configuration use DlnSpiMasterGetMode().

  • SPI Master Interface Data Transfer

    • The data is transmitted from master to slave device by MOSI (Master Output Slave Input) line. The MOSI logic signal is always generated by the master device and supplies the data from master to slave. When the data is transmitted from slave to master device the MISO (Master Input, Slave Output) line is used instead. The MISO logic signal is always sent by the slave device. MISO is the SPI data coming from the slave device back to the master device. MISO changes state at SCK edges. In SPI Master Interface mode to transmit data you can use the following functions: DlnSpiMasterReadWrite() and DlnSpiMasterReadWrite16().

    For multiple slave devices system the master device generates a separate slave select (SS) signal for each slave device. In the independent slave configuration, there is an independent SS line for each slave device. A slave device is selected when the master device asserts its SS signal.

    The SS pin plays a main part in the SPI configuration. In master mode, the SS pin must be held high to ensure master SPI operation if this pin is configured as an input pin (or vice-versa in the Active High mode). The master device must select only one slave device at a time. To use Slave Select with SPI Bus Host Adapter use DlnSpiMasterSetSS(), DlnSpiMasterGetSS() functions. This functions use GPIO Pins with connected SS pins to select slave device to work with.